In semiconductor processing, it is sometimes easier to form vertical structures where the vertical dimensions can be accurately controlled. U.S. Pat. No. 4,740,826 to Chatterjee and U.S. Pat. No. 4,810,906 to Shah et.al., which are incorporated herein by reference, disclose integrated electronic devices wherein two vertical transistors are vertically aligned to form a CMOS inverter. Thus, a layer of P type material is formed on the surface of an N+ type substrate, followed by the formation of an N+ layer, a P+ layer, an N- layer, and a P+ layer. A trench is etched along one side of the stack and a connector is formed to the midlevel P+ and N+ layers. Another trench is formed and a gate insulator and a gate are formed therein. The gate serves as a gate for both the N-channel and P-channel transistors. The connector is used to provide an output from the connected source/drain regions of the two transistors. Thus, current flows vertically through a pair of complementary field effect transistors, which are always in series.
The concept disclosed in the above-referenced patents may be used to form CMOS inverters, and other structures, such as NOR gates, which comprise a plurality of inverters. Since the stacked transistors have connected source/drain regions, however, the formation of more complex logic elements using a similarly vertical configuration is difficult.
Therefore, a need has arisen to provide a stacked vertical transistor structure from which complex logic devices may be configured.